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ltc4214-1/ltc4214-2 1 421412f typical applicatio u applicatio s u descriptio u features the ltc ? 4214 negative voltage hot swap tm controller allows a board to be safely inserted and removed from a live backplane. output current is controlled by three stages of current limiting: a timed circuit breaker, active current limiting and a fast feedforward path that limits peak current under worst-case catastrophic fault conditions. adjustable undervoltage and overvoltage detectors dis- connect the load whenever the input supply exceeds the desired operating range. the ltc4214 controls negative supplies ranging from near zero to C16v. a multifunction timer delays initial start-up and controls the circuit breakers response time. this response time is accelerated by sensing excessive mosfet drain voltage, keeping the mosfet within its safe operating area (soa). an adjust- able soft-start circuit controls mosfet inrush current at start-up. a power good status output can enable a power module at start-up or disable it if the circuit breaker trips. the ltc4214-1 latches off after a circuit breaker fault times out. the ltc4214-2 provides automatic retry after a fault. the ltc4214 is available in the 10-pin msop package. n hot board insertion n electronic circuit breaker n negative power supply control n central office switching n high availability servers n disk arrays n optical networking/switching n ecl , ltc and lt are registered trademarks of linear technology corporation. n allows safe board insertion and removal from a live backplane n controls supplies from 0v to C16v n adjustable analog current limit with circuit breaker timer n fast response time limits peak fault current n adjustable soft-start current limit n adjustable timer with drain voltage accelerated response n adjustable undervoltage/overvoltage protection n ltc4214-1: latch off after fault n ltc4214-2: automatic retry after fault n available in the 10-pin msop package negative low voltage hot swap controllers hot swap is a trademark of linear technology corporation. C 5.2v/5a ecl supply hot swap controller start-up behavior gate 5v/div sense 20mv/div v out 5v/div pwrgd 5v/div 4214 ta02 4214 ta01 gnd 3.3v uv/ov v ee v in sense ss timer gate pwrgd ltc4214-1 34k 1% 10 470 2k 100nf 32.4k 1% 5.6nf smaj7a push reset 3.3nf 10nf C5.2v 0.01 irf7413 gnd en C5.2v ecl 10 1 9, 8 10 3 7 2 6 4 5 1nf 0.1 f c load 100 f gnd (short pin) + bss138 75k 22 drain
ltc4214-1/ltc4214-2 2 421412f symbol parameter conditions min typ max units v in supply voltage l 616v i in v in supply current uv = ov = 2.5v l 0.8 2 ma v lko v in undervoltage lockout coming out of uvlo (rising v in ) l 5.1 5.6 v v lkh v in undervoltage lockout hysteresis 0.3 v v cb circuit breaker current limit voltage v cb = (v sense C v ee ) l 44 50 56 mv v acl analog current limit voltage v acl = (v sense C v ee ), ss = open l 60 70 80 mv v fcl fast current limit voltage v fcl = (v sense C v ee ) l 150 200 300 mv v ss ss voltage after end of ss timing cycle 1.6 v r ss ss output impedance 73 k w i ss ss pin current uv = ov = 2.5v, v sense = v ee , v ss = 0v (sourcing) C22 m a uv = ov = 0v, v sense = v ee , v ss = 1v (sinking) 14 ma v os analog current limit offset voltage 10 mv v acl +v os ratio (v acl + v os ) to ss voltage 0.05 v/v v ss i gate gate pin output current v sense = v ee , v gate = 0v (sourcing) l C30 C50 C70 m a v sense C v ee = 0.15v, v gate = 3v (sinking) 17 ma v sense C v ee = 0.3v, v gate = 1v (sinking) 190 ma v gate external mosfet gate drive v gate C v ee l 10 11 12 v v gateh gate high threshold v gateh = v in C v gate for pwrgd status 2.8 v v gatel gate low threshold (before gate ramp-up) 0.5 v v uvhi uv pin threshold uv rising l 2.137 2.25 2.363 v v uvhst uv pin hysteresis l 0.22 0.25 0.28 v v ovhi ov pin threshold ov rising l 2.85 3 3.15 v v ovhst ov pin hysteresis l 0.12 0.15 0.18 v v in ............................................................ C 0.3v to 17v input/output pins (except sense and drain) voltage ..........C 0.3v to 17v sense pin voltage ................................... C 0.6v to 17v current out of sense pin (20 m s pulse) ........... C 200ma drain pin minimum voltage .............................. C 0.3v current into drain pin (100 m s pulse) ................... 5ma maximum junction temperature .......................... 125 c operating temperature range ltc4214-1c/ltc4214-2c ....................... 0 c to 70 c ltc4214-1i/ltc4214-2i ................... C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c order part number ms part marking consult ltc marketing for parts specified with wider operating temperature ranges. ltabh ltabk ltabj ltabl ltc4214-1cms ltc4214-2cms ltc4214-1ims ltc4214-2ims absolute axi u rati gs w ww u package/order i for atio uu w all voltages referred to v ee (note 1) electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 12v, uv = ov = 2.5v unless otherwise noted. (note 2) t jmax = 125 c, q ja = 160 c/w 1 2 3 4 5 v in pwrgd ss sense v ee 10 9 8 7 6 timer uv ov drain gate top view ms package 10-lead plastic msop
ltc4214-1/ltc4214-2 3 421412f i sense sense pin input current v sense = 50mv l C15 C30 m a i inp uv, ov pin input current uv = ov = 2.5v l 0.1 1 m a v tmrh timer pin voltage high threshold 3v v tmrl timer pin voltage low threshold 1.7 v i tmr timer pin current timer on (initial cycle/latchoff/ C5 m a shutdown cooling, sourcing), v tmr = 2.2v timer off (initial cycle, sinking), v tmr = 2.2v 28 ma timer on (circuit breaker, sourcing, C40 m a i drn = 0 m a), v tmr = 2.2v timer on (circuit breaker, sourcing, C200 m a i drn = 20 m a), v tmr = 2.2v timer off (circuit breaker/ 5 m a shutdown cooling, sinking), v tmr = 2.2v d i tmracc [(i tmr at i drn = 20 m a) C (i tmr at i drn = 0 m a)] timer on (circuit breaker with i drn = 20 m a) 8 m a/ m a d i drn 20 m a v drnl drain pin voltage low threshold for pwrgd status l 1.109 1.232 1.355 v i drnl drain leakage current v drain = 2.5v 0.1 1 m a v drncl drain pin clamp voltage i drn = 20 m a 3.5 4.2 5 v v pgl pwrgd output low voltage i pg = 1.6ma l 0.2 0.4 v i pg = 5ma l 1.1 v i pgh pwrgd pull-up current v pwrgd = 0v (sourcing) l C30 C50 C70 m a t ss ss default ramp period ss pin floating, v ss ramps from 0.2v to 1.4v 130 m s t pllug uv low to gate low 0.4 m s t phlog ov high to gate low 0.4 m s electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v in = 12v, uv = ov = 2.5v unless otherwise noted. (note 2) symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to v ee unless otherwise specified. typical perfor a ce characteristics uw temperature ( c) i in ( a) 800 900 1000 4214 g01 700 600 400 500 1200 1100 ?5 105 ?5 25 65 ?5 125 54585 v in = 12v v in (v) i in (ma) 0.8 1.0 1.2 4214 g02 0.6 0.4 0 0.2 1.6 1.4 018 16 4812 220 61014 t a = ?0 c t a = 25 c t a = 85 c t a = 125 c temperature ( c) ?5 v lko (v) 6 5.8 5.6 5.4 5.2 5 4.8 4.6 4.4 4.2 4 ?5 25 45 125 4214 g03 ?5 5 65 85 105 i in vs temperature i in vs v in undervoltage lockout v lko vs temperature all voltages are referenced to v ee unless otherwise specified.
ltc4214-1/ltc4214-2 4 421412f temperature ( c) v fcl (mv) 4214 g07 ?5 ?5 25 45 125 ?5 5 65 85 105 300 275 250 225 200 175 150 v in = 12v undervoltage lockout hysteresis v lkh vs temperature typical perfor a ce characteristics uw temperature ( c) i ss (ma) 4214 g10 ?5 ?5 25 45 125 ?5 5 65 85 105 v in = 12v uv = ov = v sense = v ee v ss = 1v 25 20 15 10 5 0 temperature ( c) ?5 v os (mv) 11.0 10.8 10.6 10.4 10.2 10.0 9.8 9.6 9.4 9.2 9.0 ?5 25 45 125 4214 g11 ?5 5 65 85 105 v in = 12v temperature ( c) ?5 (v acl + v os )/v ss (v/v) 0.060 0.058 0.056 0.054 0.052 0.050 0.048 0.046 0.044 0.042 0.040 ?5 25 45 125 4214 g12 ?5 5 65 85 105 v in = 12v temperature ( c) v lkh (v) 4214 g04 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 C55 C15 25 45 125 C35 5 65 85 105 temperature ( c) v cb (mv) 4214 g05 ?5 ?5 25 45 125 ?5 5 65 85 105 56 54 52 50 48 46 44 v in = 12v temperature ( c) v acl (mv) 4214 g06 ?5 ?5 25 45 125 ?5 5 65 85 105 v in = 12v 80 78 76 74 72 70 68 66 64 62 60 temperature ( c) v ss (v) 4214 g08 ?5 ?5 25 45 125 ?5 5 65 85 105 v in = 12v 1.80 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 temperature ( c) ?5 r ss (k ) 85 83 81 79 77 75 73 71 69 67 65 ?5 25 45 125 4214 g09 ?5 5 65 85 105 v in = 12v circuit breaker current limit voltage v cb vs temperature analog current limit voltage v acl vs temperature fast current limit voltage v fcl vs temperature v ss vs temperature r ss vs temperature i ss (sinking) vs temperature v os vs temperature (v acl + v os )/v ss vs temperature all voltages are referenced to v ee unless otherwise specified.
ltc4214-1/ltc4214-2 5 421412f temperature ( c) ?5 i gate ( a) 60 58 56 54 52 50 48 46 44 42 40 ?5 25 45 125 4214 g13 ?5 5 65 85 105 v in = 12v uv/ov = 2.5v timer = 0v v sense = v ee v gate = 0v temperature ( c) i gate (ma) 4214 g14 ?5 ?5 25 45 125 ?5 5 65 85 105 30 25 20 15 10 5 0 v in = 12v uv/ov = 2.5v timer = 0v v sense ?v ee = 0.15v v gate = 3v temperature ( c) ?5 i gate (ma) 200 250 300 105 4214 g15 150 100 0 ?5 25 65 ?5 125 54585 50 400 350 v in = 12v uv/ov = 2.5v timer = 0v v sense ?v ee = 0.3v v gate = 1v temperature ( c) ?5 v gate (v) 12.0 11.8 11.6 11.4 11.2 11.0 10.8 10.6 10.4 10.2 10.0 ?5 25 45 125 4214 g16 ?5 5 65 85 105 v in = 12v uv/ov = 2.5v timer = 0v v sense = v ee temperature ( c) v gateh (v) 2.8 3.0 3.2 4214 g17 2.6 2.4 2.0 2.2 3.6 3.4 ?5 105 ?5 25 65 ?5 125 54585 v in = 12v uv/ov = 2.5v v gateh = v in ?v gate temperature ( c) v gatel (v) 0.4 0.5 0.6 4214 g18 0.3 0.2 0 0.1 0.8 0.7 ?5 105 ?5 25 65 ?5 125 54585 v in = 12v uv/ov = 2.5v timer = 0v gate threshold before ramp-up typical perfor a ce characteristics uw temperature ( c) v uvhi (v) 4214 g19 ?5 ?5 25 45 125 ?5 5 65 85 105 2.40 2.35 2.30 2.25 2.20 2.15 2.10 v in = 12v temperature ( c) v uvhst (v) 4214 g20 C55 C15 25 45 125 C35 5 65 85 105 0.28 0.27 0.26 0.25 0.24 0.23 0.22 v in = 12v temperature ( c) v ovhi (v) 4214 g21 ?5 ?5 25 45 125 ?5 5 65 85 105 3.15 3.10 3.05 3.00 2.95 2.90 2.85 v in = 12v i gate (sourcing) vs temperature i gate (acl, sinking) vs temperature i gate (fcl, sinking) vs temperature v gate vs temperature v gateh vs temperature v gatel vs temperature v uvhi vs temperature v uvhst vs temperature v ovhi vs temperature all voltages are referenced to v ee unless otherwise specified.
ltc4214-1/ltc4214-2 6 421412f typical perfor a ce characteristics uw temperature ( c) v ovhst (v) 4214 g22 C55 C15 25 45 125 C35 5 65 85 105 0.18 0.17 0.16 0.15 0.14 0.13 0.12 v in = 12v temperature ( c) i sense ( a) 4214 g23 ?5 ?5 25 45 125 ?5 5 65 85 105 0 ? ?0 ?5 ?0 ?5 ?0 v in = 12v uv/ov = 2.5v timer = 0v gate = high v sense ?v ee = 50mv (v sense ?v ee ) (v) ?.5 1000 ? sense (ma) 10 0.01 ?.5 0.5 1.0 4214 g24 100 0.10 1 ?.0 0 1.5 2.0 v in = 12v uv/ov = 2.5v timer = 0v gate = high t a = 25 c temperature ( c) timer threshold (v) 4214 g25 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 ?5 ?5 25 45 125 ?5 5 65 85 105 v in = 12v v tmrh v tmrl temperature ( c) i tmr ( a) 5.0 5.5 6.0 4214 g26 4.5 4.0 3.0 3.5 7.0 6.5 ?5 105 ?5 25 65 ?5 125 54585 v in = 12v timer = 2.2v temperature ( c) i tmr (ma) 30 35 40 4214 g27 25 20 10 15 50 45 ?5 105 ?5 25 65 ?5 125 54585 v in = 12v timer = 2.2v temperature ( c) i tmr ( a) 40 45 50 4214 g28 35 30 20 25 60 55 ?5 105 ?5 25 65 ?5 125 54585 v in = 12v timer = 2.2v i drn = 0 a temperature ( c) i tmr ( a) 200 205 210 4214 g29 195 190 180 185 220 215 ?5 105 ?5 25 65 ?5 125 54585 v in = 12v timer = 2.2v i drn = 20 a temperature ( c) i tmr ( a) 5.0 5.5 6.0 4214 g30 4.5 4.0 3.0 3.5 7.0 6.5 ?5 105 ?5 25 65 ?5 125 54585 v in = 12v timer = 2.2v v ovhst vs temperature i sense vs temperature i sense vs (v sense C v ee ) timer threshold vs temperature i tmr (initial cycle, sourcing) vs temperature i tmr (initial cycle, sinking) vs temperature i tmr (circuit breaker, sourcing) vs temperature i tmr (circuit breaker, i drn = 20 m a, sourcing) vs temperature i tmr (cooling cycle, sinking) vs temperature all voltages are referenced to v ee unless otherwise specified.
ltc4214-1/ltc4214-2 7 421412f typical perfor a ce characteristics uw i drn (ma) 0.1 i tmr (ma) 1 0.001 0.1 1 10 4214 g31 0.01 0.01 10 v in = 12v timer = 2.2v t a = 25 c temperature ( c) ?5 ( ? i tmracc / ? i drn ( a/ a) 9.0 8.8 8.6 8.4 8.2 8.0 7.8 7.6 7.4 7.2 7.0 ?5 25 45 125 4214 g32 ?5 5 65 85 105 v in = 12v timer on (circuit breaking, i drn = 20 a) v drain (v) i drn (ma) 4214 g33 0.1 1 10 0.01 0.001 0.00001 0.0001 100 04812 216 61014 t a = ?0 c t a = 25 c t a = 85 c t a = 125 c v in = 12v temperature ( c) v drnl (v) 4214 g34 ?5 ?5 25 45 125 ?5 5 65 85 105 1.40 1.35 1.30 1.25 1.20 1.15 1.10 v in = 12v for pwrgd status temperature ( c) ?5 v drncl (v) ?5 25 45 125 4214 g35 ?5 5 65 85 105 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 3.4 3.2 v in = 12v i drn = 20 a temperature ( c) v pgl (v) 4214 g36 ?5 ?5 25 45 125 ?5 5 65 85 105 v in = 12v i pg = 10ma i pg = 5ma i pg = 1.6ma 2.5 2.0 1.5 1.0 0.5 0 temperature ( c) i pgh ( a) 50 55 60 4214 g37 45 40 30 35 70 65 ?5 105 ?5 25 65 ?5 125 54585 v in = 12v v pwrgd = 0v temperature ( c) t ss ( s) 4214 g38 ?5 ?5 25 45 125 ?5 5 65 85 105 160 150 140 130 120 110 100 v in = 12v ss pin floating, v ss ramps from 0.2v to 1.4v temperature ( c) delay ( s) 0.4 0.5 0.6 4214 g39 0.3 0.2 0 0.1 0.8 0.7 ?5 105 ?5 25 65 ?5 125 54585 v in = 12v t phlog t pllug i tmr (circuit breaker, sourcing) vs i drn d i tmracc / d i drn vs temperature i drn vs v drain v drnl vs temperature v drncl vs temperature v pgl vs temperature i pgh (sourcing) vs temperature t ss vs temperature t pllug and t phlog vs temperature all voltages are referenced to v ee unless otherwise specified.
ltc4214-1/ltc4214-2 8 421412f v in (pin 1): positive supply input. connect this pin to the positive side of the supply via a resistor. an internal undervoltage lockout (uvlo) circuit holds gate low until the v in pin is greater than v lko (5.1v), overriding uv and ov. if uv is high, ov is low and v in comes out of uvlo, timer starts an initial timing cycle before initiating a gate ramp-up. if v in drops below approximately 4.8v, gate pulls low immediately. pwrgd (pin 2): power good status output. at start-up, pwrgd latches low if drain is below 1.232v and gate is within 2.8v of v in . pwrgd status is reset by uv, v in (uvlo) or a circuit breaker fault timeout. this pin is internally pulled high by a 50 m a current source. ss (pin 3): soft-start pin. this pin is used to ramp inrush current during start up, thereby effecting control over di/ dt. a 20x attenuated version of the ss pin voltage is presented to the current limit amplifier. this attenuated voltage limits the mosfets drain current through the sense resistor during the soft-start current limiting. at the beginning of a start-up cycle, the ss capacitor (c ss ) is ramped by a 22 m a current source. the gate pin is held low until ss exceeds 20 ? v os = 0.2v. ss is internally shunted by a 73k resistor (r ss ) which limits the ss pin voltage to 1.6v. this corresponds to an analog current limit sense voltage of 70mv. if the ss capacitor is omitted, the ss pin ramps from 0v to 1.6v in about 220 m s. the ss pin is pulled low under any of the following conditions: in uvlo, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. sense (pin 4): circuit breaker/current limit sense pin. load current is monitored by a sense resistor r s con- nected between sense and v ee , and controlled in three steps. if sense exceeds v cb (50mv), the circuit breaker comparator activates a (40 m a + 8 ? i drn ) timer pull-up current. if sense exceeds v acl (70mv), the analog cur- rent limit amplifier pulls gate down to regulate the mosfet current at v acl /r s . in the event of a catastrophic short- circuit, sense may overshoot 70mv. if sense reaches v fcl (200mv), the fast current limit comparator pulls gate low with a strong pull-down. to disable the circuit breaker and current limit functions, connect sense to v ee . v ee (pin 5): negative supply voltage input. connect this pin to the negative side of the power supply. gate (pin 6): n-channel mosfet gate drive output. this pin is pulled high by a 50 m a current source. gate is pulled low by invalid conditions at v in (uvlo), uv, ov, or a circuit breaker fault timeout. gate is actively servoed to control the fault current as measured at sense. a compensation capacitor at gate stabilizes this loop. a comparator monitors gate to ensure that it is low before allowing an initial timing cycle, gate ramp-up after an overvoltage event or restart after a current limit fault. during gate start-up, a second comparator detects if gate is within 2.8v of v in before pwrgd is set. drain (pin 7): drain sense input. drain measures the drain-source voltage of the external n-channel mosfet switch for two purposes: first, a comparator detects when v ds < 1.232v and together with the gate high compara- tor, controls the status of the pwrgd output. second, if v ds is greater than the drain clamp of approximately 4.2v (v drncl ), the current through resistor r d is multi- plied by 8 and added to the timers 40 m a pull-up current during a circuit breaker fault cycle. this reduces the fault time and mosfet heating under conditions of high dissipation. ov (pin 8): overvoltage input. the active high threshold at the ov pin is set at 3v with respect to v ee and exhibits 0.15v hysteresis. if ov > 3v, gate pulls low. when ov returns below 2.85v, gate start-up begins without an initial timing cycle. if an overvoltage condition occurs in the middle of an initial timing cycle, the initial timing cycle is restarted after the overvoltage condition goes away. an overvoltage condition does not reset the pwrgd flag. the internal uvlo at v in always overrides ov. a 1nf to 10nf capacitor at ov prevents transients and switching noise from affecting the ov thresholds and prevents glitches at the gate pin. pi fu ctio s uuu
ltc4214-1/ltc4214-2 9 421412f uv (pin 9): undervoltage input. the active high threshold at the uv pin is set at 2.25v with respect to v ee and exhibits 0.25v hysteresis. if uv < 2v, pwrgd pulls high, both gate and timer pull low. if uv rises above 2.25v, this initiates an initial timing cycle followed by gate start-up. the internal uvlo at v in always overrides uv. a low at uv resets an internal fault latch. a 1nf to 10nf capacitor at uv prevents transients and switching noise from affecting the uv thresholds and prevents glitches at the gate pin. timer (pin 10): timer input. timer is used to generate an initial timing delay at start-up and to delay shutdown in the event of an output overload (circuit breaker fault). timer starts an initial timing cycle when the following conditions are met: uv is high, ov is low, v in clears uvlo, timer pin is low, gate is lower than v gatel , ss < 0.2v, and v sense C v ee < v cb . a pull-up current of 5 m a then charges c t , generating a time delay. if c t charges to v tmrh (3v), the timing cycle terminates, timer quickly pulls low and gate is activated. if sense exceeds 50mv while gate is high, a circuit breaker cycle begins with a 40 m a pull-up current charging c t . if drain is approximately 4.2v during this cycle, the timer pull-up has an additional current of 8 ? i drn . if sense drops below 50mv before timer reaches 3v, a 5 m a pull- down current slowly discharges the c t . in the event that c t eventually integrates up to the v tmrh threshold, the circuit breaker trips, gate quickly pulls low and pwrgd pulls high. the ltc4214-1 timer pin latches high with a 5 m a pull-up source. this latched fault is cleared by either pulling timer low with an external device or by pulling uv below 2v. the ltc4214-2 starts a shutdown cooling cycle following an overcurrent fault. this cycle consists of 4 discharging ramps and 3 charging ramps. the charging and discharging currents are 5 m a and timer ramps between its 1.7v and 3v thresholds. at the completion of a shutdown cooling cycle, the ltc4214-2 attempts a start- up cycle. pi fu ctio s uuu
ltc4214-1/ltc4214-2 10 421412f block diagra w C + 4214 bd C + C + C + C + + C + C v in v in v ee v ee r ss v ee v ee v ee 0.5v v ee v ee 5 a 5 a v in v ee v in 3v 50 a 40 a v in 22 a 69.35k timer 3v 2.25v 3v 1.7v + C + C 1.232v v ee v ee v os = 10mv v in 2.8v C + uv gate sense v in v ee 50 a pwrgd drain ov ss v in cb 50mv + C C + fcl 200mv + C acl 3.65k + C 1 1 8 1 logic 1 8 9 10 3 5 4 6 2 7
ltc4214-1/ltc4214-2 11 421412f hot circuit insertion when circuit boards are inserted into a live backplane, the supply bypass capacitors can draw huge transient cur- rents from the power bus as they charge. the flow of current damages the connector pins and glitches the power bus, causing other boards in the system to reset. the ltc4214 is designed to turn on a circuit board supply in a controlled manner, allowing insertion or removal without glitches or connector damage. initial start-up the ltc4214 resides on a removable circuit board and controls the path between the connector and the load with an external mosfet switch (see figure 1). both inrush control and short-circuit protection are provided by the mosfet. a detailed schematic is shown in figure 2. C 12v and gnd receive power through the longest connector pins and are the first to connect when the board is inserted. the gate pin holds the mosfet off during this time. uv/ov determines whether or not the mosfet should be turned on based upon internal high accuracy thresholds and an external divider. uv/ov does double duty by also monitor- ing whether or not the connector is seated. the top of the divider detects gnd by way of a short connector pin that is the last to mate during the insertion sequence. interlock conditions a start-up sequence commences once these interlock conditions are met. 1. the input voltage v in exceeds 5.1v (uvlo). 2. the voltage at uv > 2.25v. operatio u figure 1. basic ltc4214 hot swap topology figure 2. C12v, 2a hot swap controller 3. the voltage at ov < 2.85v. 4. the (sense C v ee ) voltage is < 50mv (v cb ). 5. the voltage at ss is < 0.2v (20 ? v os ). 6. the voltage on the timer capacitor (c t ) is < 1.7v (v tmrl ). 7. the voltage at gate is < 0.5v (v gatel ). the first three conditions are continuously monitored and the latter four are checked prior to initial timing or gate ramp-up. upon exiting an ov condition, the timer pin voltage requirement is inhibited. details are described in the applications information, timing waveforms section. timer begins the start-up sequence by sourcing 5 m a into c t . if v in , uv or ov falls out of range, the start-up cycle stops and timer discharges c t to less than 1.7v, then waits until the aforementioned conditions are once again met. if c t successfully charges to 3v, timer pulls low and both ss and gate pins are released. gate sources 50 m a (i gate ), charging the mosfet gate and associated capacitance. the ss voltage ramp limits v sense to control the inrush current. pwrgd pulls active low when gate is within 2.8v of v in and drain is lower than v drnl . two modes of operation are possible during the time the mosfet is first turning on, depending on the values of external components, mosfet characteristics and nomi- nal design current. one possibility is that the mosfet will 4214 f01 ltc4214 c load plug-in board backplane gnd ?2v long long + load 4214 f02 gnd ?2v gnd v out en uv ov pwrgd timer v ee v in sense gate ss drain ltc4214-1 r1 121k 1% r2 32.4k 1% r d 475k c t 47nf z1: smaj15a c ss 22nf c c 10nf r s 0.025 q1 irf7413 r c 10 r4 10k c1 1nf c in 0.1 f 1 2 9 8 10 3 7 6 4 5 z1 c x 100nf r x 10 r in 470 r3 10k c load 100 f typ long long short +
ltc4214-1/ltc4214-2 12 421412f operatio u turn on gradually so that the inrush into the load capaci- tance remains a low value. the output will simply ramp to C12v and the ltc4214 will fully enhance the mosfet. a second possibility is that the load current exceeds the soft-start current limit threshold of [v ss (t)/20 C v os ]/r s . in this case the ltc4214 will ramp the output by sourcing soft-start limited current into the load capacitance. if the soft-start voltage is below 1.2v, the circuit breaker timer is held low. above 1.2v, timer ramps up. it is important to set the timer delay so that, regardless of which start-up mode is used, the timer ramp is less than one circuit breaker delay time. if this condition is not met, the ltc4214-1 may shut down after one circuit breaker delay time whereas the ltc4214-2 may continue to autoretry. board removal if the board is withdrawn from the card cage, the uv/ov divider is the first to lose connection. this shuts off the mosfet and commutates the flow of current in the connector. when the power pins subsequently separate, there is no arcing. current control three levels of protection handle short-circuit and over- load conditions. load current is monitored by sense and resistor r s . there are three distinct thresholds at sense: 50mv for a timed circuit breaker function; 70mv for an analog current limit loop; and 200mv for a fast, feedforward comparator which limits peak current in the event of a catastrophic short-circuit. if, owing to an output overload, the voltage drop across r s exceeds 50mv, timer sources 40 m a into c t . c t eventually charges to a 3v threshold and the ltc4214 shuts off. if the overload goes away before c t reaches 3v and sense measures less than 50mv, c t slowly dis- charges (5 m a). in this way the ltc4214s circuit breaker function responds to low duty cycle overloads and ac- counts for fast heating and slow cooling characteristics of the mosfet. higher overloads are handled by an analog current limit loop. if the drop across r s reaches 70mv, the current limiting loop servos the mosfet gate and maintains a constant output current of 70mv/r s . in current limit mode, v out typically rises and this increases mosfet heating. if v out > v drncl (4.2v), connecting an external resistor, r d , between v out and drain allows the fault timing cycle to be shortened by accelerating the charging of the timer capacitor. the timer pull-up current is increased by 8 ? i drn . note that because sense > 50mv, timer charges c t during this time and the ltc4214 will eventually shut down. low impedance failures on the load side of the ltc4214 can produce high current slew rates. under these condi- tions, overshoot is inevitable. a fast sense comparator with a threshold of 200mv detects overshoot and pulls gate low much harder and hence much faster than the weaker current limit loop. the 70mv/r s current limit loop then takes over and servos the current as previously described. as before, timer runs and shuts down the ltc4214 when c t reaches 3v. if c t reaches 3v, the ltc4214-1 latches off with a 5 m a pull-up current source whereas the ltc4214-2 starts a shutdown cooling cycle. the ltc4214-1 circuit breaker latch is reset by either pulling uv momentarily low or drop- ping the input voltage v in below the internal uvlo thresh- old of 4.8v or pulling timer momentarily low with a switch. the ltc4214-2 retries after its shutdown cooling cycle. although short-circuits are the most obvious fault type, several operating conditions may invoke overcurrent pro- tection. noise spikes from the backplane or load, transient currents caused by faults on adjacent circuit boards shar- ing the same power bus or the insertion of non-hot- swappable products could cause higher than anticipated input current and temporary detection of an overcurrent condition. the action of timer and c t rejects these events allowing the ltc4214 to ride out temporary overloads and disturbances that could trip a simple current comparator and, in some cases, blow a fuse.
ltc4214-1/ltc4214-2 13 421412f applicatio s i for atio wu u u supply voltage the ltc4214 requires a (v in C v ee ) voltage of 6v to 16v to function. this can be derived from gnd and C12v of a C12v system or the 3.3v and C5.2v of a C5.2v system. the positive supply is connected to v in via an rc network so that the ltc4214 can have a usable v in during load short or other transient events when (v in C v ee ) glitches below 6v. internal undervoltage lockout (uvlo) a hysteretic comparator, uvlo, monitors v in for undervoltage. the thresholds are defined by v lko and its hysteresis, v lkh . when v in rises above 5.1v (v lko ) the chip is enabled; below 4.8v (v lko C v lkh ) it is disabled and gate is pulled low. the uvlo function at v in should not be confused with the uv/ov pins. these are completely separate functions. uv/ov comparators an uv hysteretic comparator detects undervoltage condi- tions at the uv pin, with the following thresholds: uv low-to-high (v uvhi ) = 2.25v uv high-to-low (v uvhi C v uvhst ) = 2v an ov hysteretic comparator detects overvoltage condi- tions at the ov pin, with the following thresholds: ov low-to-high (v ovhi ) = 3v ov high-to-low (v ovhi C v 0vhst ) = 2.85v in figure 2, a divider (r1-r2) is used to scale the supply voltage of 12v 10%. using r1 = 121k and r2 = 32.4k gives a typical operating range of 10.7v to 13.5v. the under and overvoltage shutdown thresholds are then 9.5v to 14.2v. 1% divider resistors are recommended to pre- serve threshold accuracy. the r1-r2 divider values shown in figure 2 set a standing current of slightly more than 75 m a and define an imped- ance at uv/ov of 25k w . in most applications, 25k w impedance coupled with 250mv uv hysteresis makes the ltc4214 insensitive to noise. if more noise immunity is desired, add a 1nf to 10nf filter capacitor from uv/ov to v ee . separate uv and ov pins can be used for a wider operating range such as 10v to 14v as shown in figure 3. other combinations are possible with different resistor arrangements. figure 3. C 12v/2a application with wider input operating range 4214 f03 gnd uv z1 ov v ee v in sense ss timer gate pwrgd drain ltc4214-1 r1 124k 1% r x 10 r in 470 c x 100nf r3 32.4k 1% r2 3.65k 1% c t 47nf c ss 22nf c c 10nf ?2v r s 0.025 q1 irf7413 r c 10 r4 100k q2 nds0605 1 9 8 10 3 2 7 6 4 5 c2 1nf c in 0.1 f c l 100 f gnd (short pin) + r d 475k en r pulldn 10k v out gnd z1: smaj15a
ltc4214-1/ltc4214-2 14 421412f uv/ov operation a low input to the uv comparator will reset the ltc4214 and pull the gate and timer pins low. a low-to-high uv transition will initiate an initial timing sequence if the other interlock conditions are met. a high-to-low transition in the uv comparator immediately shuts down the ltc4214, pulls the mosfet gate low and resets the latched pwrgd high. overvoltage conditions detected by the ov comparator will also pull gate low, thereby shutting down the load. however, it will not reset the circuit breaker timer, pwrgd flag or shutdown cooling timer. returning the supply voltage to an acceptable range restarts the gate pin if all the interlock conditions except timer are met. only during the initial timing cycle does an ov condition reset the timer. drain connecting an external resistor, r d , to the dual function drain pin allows v out sensing without it being damaged by large voltage transients. below 3v, negligible pin leak- age allows a drain low comparator to detect v out less than 1.232v (v drnl ). this condition, together with the gate low comparator, sets the pwrgd flag. if v out > v drncl (4.2v), the drain pin is clamped at about 4.2v and the current flowing in r d is given by: i vv r drn out drncl d ? - (1) this current is scaled up 8 times during a circuit breaker fault and is added to the nominal 40 m a timer current. this accelerates the fault timer pull-up when the mosfets drain-source voltage exceeds 4.2v and effectively short- ens the mosfet heating duration. timer the operation of the timer pin is somewhat complex as it handles several key functions. a capacitor c t is used at timer to provide timing for the ltc4214. four different charging and discharging modes are available at timer: 1) a 5 m a slow charge; initial timing and shutdown cooling delay. 2) a (40 m a + 8 ? i drn ) fast charge; circuit breaker delay. 3) a 5 m a slow discharge; circuit breaker "cool off" and shutdown cooling. 4) low impedance switch; resets the timer capacitor after an initial timing delay, in uvlo, in uv and in ov during initial timing. for initial start-up, the 5 m a pull-up is used. the low impedance switch is turned off and the 5 m a current source is enabled when the interlock conditions are met. c t charges to 3v in a time period given by: t vc a t = m 3 5 (2) when c t reaches 3v (v tmrh ), the low impedance switch turns on and discharges c t . a gate start-up cycle begins and both ss and gate are released. circuit breaker timer operation if the sense pin detects more than a 50mv drop across r s , the timer pin charges c t with (40 m a + 8 ? i drn ). if c t charges to 3v, the gate pin pulls low and the ltc4214-1 latches off while the ltc4214-2 starts a shutdown cooling cycle. the ltc4214-1 remains latched off until the uv pin is momentarily pulsed low or timer is momentarily discharged low by an external switch or v in dips below uvlo and is then restored. the circuit breaker timeout period is given by: t vc ai t drn = m+ 3 40 8 (3) if v out < 3v, an internal pmos device isolates any drain pin leakage current, making i drn = 0 m a in equation (3). if v out > 4.2v (v drncl ) during the circuit breaker fault period, the charging of c t accelerates by 8 ? i drn of equation (1). intermittent overloads may exceed the 50mv threshold at sense, but, if their duration is sufficiently short, timer will not reach 3v and the ltc4214 will not shut the external applicatio s i for atio wu u u
ltc4214-1/ltc4214-2 15 421412f mosfet off. to handle this situation, the timer dis- charges c t slowly with a 5 m a pull-down whenever the sense voltage is less than 50mv. therefore, any intermit- tent overload with v out < 3v and an aggregate duty cycle of 12.5% or more will eventually trip the circuit breaker and shut down the ltc4214. figure 4 shows the circuit breaker response time in seconds normalized to 1 m f for i drn = 0 m a. the asymmetric charging and discharging of c t is a fair gauge of mosfet heating. the normalized circuit response time is estimated by t cf id t drn () m = + () - [] 3 40 8 5 (4) pull-down cycles and three 5 m a pull-up cycles occur between the 1.7v and 3v thresholds, creating a time interval given by: t vc a shutdown t = m 713 5 . (5) at the 1.7v threshold of the last pull-down cycle, a gate ramp-up is attempted. soft-start soft-start limits the inrush current profile during gate start-up. unduly long soft-start intervals can exceed the mosfets soa rating if powering up into an active load. if ss floats, an internal current source ramps ss from 0v to 1.6v in about 220 m s. connecting an external capacitor c ss from ss to ground modifies the ramp to approximate an rc response of: vtv e ss ss t rc ss ss () ?- ? ? ? ? ? ? - ? ? ? ? 1 (6) an internal resistor divider (69.35k/3.65k) scales v ss (t) down by 20 times to give the analog current limit thresh- old: vt vt v acl ss os () () =- 20 (7) this allows the inrush current to be limited to v acl (t)/r s . the offset voltage, v os (10mv), ensures c ss is sufficiently discharged and the acl amplifier is in current limit before gate start-up. ss is pulled low under any of the following conditions: in uvlo, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. applicatio s i for atio wu u u fault duty cycle (%) 0.1 normalized response time (s/ f) 1 10 100 010 405060708090 0.01 20 30 100 4214 f04 = 3 [(40 + 8 ?i drn ) ?d ?5] t c t ( f) i drn = 0 a figure 4. circuit-breaker response time shutdown cooling cycle for the ltc4214-1 (latchoff version), timer latches high with a 5 m a pull-up after the circuit breaker fault timer reaches 3v. for the ltc4214-2 (automatic retry version), a shutdown cooling cycle begins if timer reaches the 3v threshold. timer starts with a 5 m a pull-down until it reaches the 1.7v threshold. then, the 5 m a pull-up turns back on until timer reaches the 3v threshold. four 5 m a
ltc4214-1/ltc4214-2 16 421412f gate gate is pulled low to v ee under any of the following conditions: in uvlo, in an undervoltage condition, in an overvoltage condition, during the initial timing cycle or when the circuit breaker fault times out. when gate turns on, a 50 m a current source charges the mosfet gate and any associated external capacitance. the gate drive is limited to no more than v in . gate-drain capacitance (c gd ) feedthrough at the first abrupt application of power can cause a gate-source voltage sufficient to turn on the mosfet. a unique circuit pulls gate low with practically no usable voltage at v in and eliminates current spikes at insertion. a large external gate-source capacitor is thus unnecessary for the purpose of compensating c gd . instead, a smaller value ( 3 5nf) capacitor c c is adequate. c c also provides compensation for the analog current limit loop. gate has two comparators: the gate low comparator looks for < 0.5v threshold prior to initial timing or a gate start-up cycle; the gate high comparator looks for < 2.8v relative to v in and, together with the drain low compara- tor, sets pwrgd status during gate start-up. sense the sense pin is monitored by the circuit breaker (cb) comparator, the analog current limit (acl) amplifier and the fast current limit (fcl) comparator. each of these three measures the potential of sense relative to v ee . when sense exceeds 50mv, the cb comparator activates the 40 m a timer pull-up. at 70mv, the acl amplifier servos the mosfet current and, at 200mv, the fcl comparator abruptly pulls gate low in an attempt to bring the mosfet current under control. if any of these conditions persists long enough for timer to charge c t to 3v (see equa- tion 3), the ltc4214 shuts down and pulls gate low. if the sense pin encounters a voltage greater than 70mv, the acl amplifier will servo gate downwards in an attempt to control the mosfet current. since gate overdrives the mosfet in normal operation, the acl amplifier needs time to discharge gate to the threshold of the mosfet. for a mild overload the acl amplifier can control the mosfet current, but in the event of a severe overload the current may overshoot. at sense = 200mv the fcl comparator takes over, quickly discharging the gate pin to near v ee potential. fcl then releases and the acl amplifier takes over. all the while timer is running. the effect of fcl is to add a nonlinear response to the control loop in favor of reducing mosfet current. owing to inductive effects in the system, fcl typically overcorrects the current limit loop and gate under- shoots. a zero in the loop (resistor r c in series with the gate capacitor) helps the acl amplifier to recover. short-circuit operation circuit behavior arising from a load side low impedance short is shown in figure 5 for the ltc4214. initially, the current overshoots the fast current limit level of v sense = 200mv (trace 2) as the gate pin works to bring v gs under control (trace 3). the overshoot glitches the backplane in the negative direction and when the current is reduced to 70mv/r s , the backplane responds by glitching in the positive direction. applicatio s i for atio wu u u figure 5. output short-circuit behavior of ltc4214 gnd with respect to ?2v 0.1ms 10v trace 1 trace 2 trace 3 trace 4 sense 0.1ms 200mv gate 0.1ms 10v timer 0.1ms 2v 4214 f05 latch off analog current limit fast current limit onset of output short circuit supply ring owing to current overshoot supply ring owing to mosfet turn-off c timer ramp
ltc4214-1/ltc4214-2 17 421412f timer commences charging c t (trace 4) while the analog current limit loop maintains the fault current at 70mv/r s , which in this case is 3.5a (trace 2). note that the back- plane voltage (trace 1) sags under load. timer pull-up is accelerated by v out . when c t reaches 3v, gate turns off, pwrgd pulls high, the load current drops to zero and the backplane rings in the positive direction. the transient associated with the gate turn off can be controlled with a snubber to reduce ringing and transient voltage suppres- sor to clip off large spikes. the choice of rc for the snubber is usually done experimentally. the value of the snubber capacitor is usually chosen between 10 to 100 times the mosfet c oss . the value of the snubber resistor is typically between 3 w to 100 w . in many cases, a simple short-circuit test can be performed to determine the component values needed. a low impedance short on one card may influence the behavior of others sharing the same backplane. the initial glitch and backplane sag as seen in figure 5 trace 1, can rob charge from output capacitors on adjacent cards. when the faulty card shuts down, current flows in to refresh the capacitors. if ltc4214s are used by the other cards, they respond by limiting the inrush current to a value of 70mv/r s . if c t is sized correctly, the capacitors will recharge long before c t times out. power good, pwrgd pwrgd latches low if gate charges up to within 2.8v of v in and drain pulls below v drnl during start-up. pwrgd is reset in uvlo, in a uv condition or if c t charges up to 3v. an overvoltage condition has no effect on pwrgd status. a 50 m a current pulls this pin high during reset. various ways of using the pwrgd pin for interfacing with a power module load are shown in the typical application as well as figures 2, 3, 18 and 19. mosfet selection the external mosfet switch must have adequate safe operating area (soa) to handle short-circuit conditions until timer times out. these considerations take prece- dence over dc current ratings. a mosfet with adequate soa for a given application can always handle the required current, but the opposite may not be true. consult the manufacturers mosfet data sheet for safe operating area and effective transient thermal impedance curves. mosfet selection is a 3-step process by assuming the absense of a soft-start capacitor. first, r s is calculated and then the time required to charge the load capacitance is determined. this timing, along with the maximum short- circuit current and maximum input voltage defines an operating point that is checked against the mosfets soa curve. to begin a design, first specify the required load current and ioad capacitance, i l and c l . the circuit breaker current trip point (v cb /r s ) should be set to accommodate the maximum load current. note that maximum input current to a dc/dc converter is expected at v supply(min) . r s is given by: r v i s cb min l max = () () (8) where v cb(min) = 44mv represents the guaranteed mini- mum circuit breaker threshold. during the initial charging process, the ltc4214 may operate the mosfet in current limit, forcing (v acl ) be- tween 60mv to 80mv across r s . the minimum inrush current is given by: i mv r inrush min s () = 60 (9) maximum short-circuit current limit is calculated using the maximum v sense . this gives i mv r shortcircuit max s () = 80 (10) the timer capacitor c t must be selected based on the slowest expected charging rate; otherwise timer might time out before the load capacitor is fully charged. a value applicatio s i for atio wu u u
ltc4214-1/ltc4214-2 18 421412f for c t is calculated based on the maximum time it takes the load capacitor to charge. that time is given by: t cv i cv i cl charge l supply max inrush min () () () == (11) the maximum current flowing in the drain pin is given by: i vv r drn max supply max drncl d () () = - (12) approximating a linear charging rate as i drn drops from i drn(max) to zero, the i drn component in equation (3) can be approximated with 0.5 ? i drn(max) . rearranging equa- tion, timer capacitor c t is given by: c tai v t cl charge drn max = m+ () () () 40 4 3 (13) returning to equation (3), the timer period is calculated and used in conjunction with v supply(max) and i shortcircuit(max) to check the soa curves of a prospec- tive mosfet. as a numerical design example, consider a 10w load, which requires 1.1a input current at C10.8v. if v supply(max) = 13.2v and c l = 100 m f, r d = 475k, equa- tion (8) gives r s = 40m w ; equation (13) gives c t = 34nf. to account for errors in r s , c t , timer current (40 m a), timer threshold (3v), r d , drain current multiplier and drain voltage clamp (v drncl ), the calculated value should be multiplied by 1.5, giving the nearest standard value of c t = 56nf. if a short-circuit occurs, a current of up to 80mv/ 40m w = 2a will flow in the mosfet for 0.9ms as dictated by c t = 56nf in equation (3). the mosfet must be selected based on this criterion. the irf7413 can handle 20v and 2a for 9ms and is safe to use in this application. computing the maximum soft-start capacitor value during soft-start to a load short is complicated by the nonlinear mosfets soa characteristics and the r ss c ss response. an overly conservative but simple approach begins with the maximum circuit breaker current, given by: i mv r cb max s () = 56 (14) from the soa curves of a prospective mosfet, determine the time allowed, t soa(max) . c ss is given by: c t r ss soa max ss = () . 161 (15) in the above example, 56mv/40m w gives 1.4a. t soa(max) for the irf7413 is 8ms for 1.4a at 30v. from equation (15), c ss = 68nf. actual board evaluation showed that c ss = 33nf was appropriate. the ratio (r ss ? c ss ) to t cl(charge) is a good gauge as a large ratio may result in the time-out period expiring. this gauge is determined empirically with board level evaluation. summary of design flow to summarize the design flow, consider the application shown in figure 2. it was designed for 12w for a C10v to C14v supply. calculate the maximum load current: 12w/10v = 1.2a; allowing for 75% converter efficiency, i in(max) = 1.6a. calculate r s : from equation (8) r s = 25m w . calculate i shortcircuit(max) : from equation (10) i shortcircuit(max) = 3.2a. select a mosfet that can handle 3.2a at 14v: irf7413. calculate c t : from equation (13) c t = 24nf. select c t = 47nf, which gives the circuit breaker time-out period t max = 0.7ms. consult mosfet soa curves: the irf7413 can handle 3.2a at 20v for 3.5ms, so it is safe to use in this application. calculate c ss : using equations (14) and (15) select c ss = 22nf. frequency compensation the ltc4214 typical frequency compensation network for the analog current limit loop is a series r c (10 w ) and c c connected to v ee . figure 6 depicts the relationship be- applicatio s i for atio wu u u
ltc4214-1/ltc4214-2 19 421412f tween the compensation capacitor c c and the mosfets c iss . the line in figure 6 is used to select a starting value for c c based upon the mosfets c iss specification. opti- mized values for c c are shown for several popular mosfets. differences in the optimized value of c c versus the starting value are small. nevertheless, compensation values should be verified by board level short-circuit testing. as seen in figure 5 previously, at the onset of a short- circuit event, the input supply voltage can ring dramati- cally owing to series inductance. if this voltage avalanches the mosfet, current continues to flow through the mosfet to the output. the analog current limit loop cannot control this current flow and therefore the loop undershoots. this effect cannot be eliminated by frequency compensation. a zener diode is required to clamp the input supply voltage and prevent mosfet avalanche. sense resistor considerations for proper circuit breaker operation, kelvin-sense pcb connections between the sense resistor and the ltc4214s v ee and sense pins are strongly recommended. the drawing in figure 7 illustrates the correct way of making connections between the ltc4214 and the sense resistor. pcb layout should be balanced and symmetrical to mini- mize wiring errors. in addition, the pcb layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. timing waveforms system power-up figure 8 details the timing waveforms for a typical power- up sequence in the case where a board is already installed in the backplane and system power is applied abruptly. at time point 1, the supply ramps up, together with uv/ov, v in , v out , drain and pwrgd. at time point 2, v in exceeds v lko and the internal logic checks for uv > v uvhi , ov < v ovhi , gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl . if all conditions are met, an initial timing cycle starts and the timer capacitor is charged by a 5 m a current source pull-up. at time point 3, timer reaches the v tmrh threshold and the initial timing cycle terminates. the timer capacitor is quickly discharged. at time point 4, the v tmrl threshold is reached and the conditions of gate < v gatel , sense < v cb and ss < 20 ? v os must be satisfied before a gate ramp-up cycle begins. ss ramps up as dictated by r ss ? c ss (as in equation 6); gate is held low by the analog current limit (acl) amplifier until ss crosses 20 ? v os . upon releasing gate, 50 m a sources into the external mosfet gate and compensation network. when the gate voltage reaches the mosfets threshold, current begins flowing into the load capacitor at time point 5. at time point 6, load current reaches the ss control level and the analog current limit loop activates. between time points 6 and 8, the gate voltage is servoed, the sense voltage is regulated at v acl (t) (equation 7) and soft-start limits the slew rate of applicatio s i for atio wu u u w current flow from load current flow to ?2v backplane sense resistor track width w: 0.03" per amp on 1 oz copper to sense to v ee 4214 f07 figure 7. making pcb connections to the sense resistor figure 6. recommended compensation capacitor c c vs mosfet c iss mosfet, c iss (pf) 0 1000 0 compensation capacitance, c c (nf) 10 25 2000 4000 5000 4214 f06 5 20 15 3000 6000 7000 irf7803 si4412ady si4410dy si4876dy si4864dy irf7413
ltc4214-1/ltc4214-2 20 421412f applicatio s i for atio wu u u gnd ?(?2v) uv/ov v in timer gate v lko sense v in clears v lko , check uv > v uvhi , ov < v ovhi , gate < v gatel , sense < v cb , ss < 20 ?v os and timer < v tmrl v out 12 3456 78 v acl v cb 9 timer clears v tmrl , check gate < v gatel , sense < v cb and ss < 20 ?v os ss drain pwrgd 40 a + 8 ?i drn 5 a 20 ?v os 50 a 10 11 v in ?v gateh v drnl v drncl 20 ?(v cb + v os ) 20 ?(v acl + v os ) v gatel v tmrl v tmrh 5 a 5 a 50 a 4214 f08 gate start-up initial timing figure 8. system power-up timing (all waveforms are referenced to v ee ) the load current. if the sense voltage (v sense C v ee ) reaches the v cb threshold at time point 7, the circuit breaker timer activates. the timer capacitor, c t , is charged by a (40 m a + 8 ? i drn ) current pull-up. as the load capacitor nears full charge, load current begins to decline. at time point 8, the load current falls and the sense voltage drops below v acl (t). the analog current limit loop shuts off and the gate pin ramps further. at time point 9, the sense voltage drops below v cb , the fault timer cycle ends, followed by a 5 m a discharge cycle (cool off). the duration between time points 7 and 9 must be shorter than one circuit breaker delay to avoid a fault time out during gate ramp-up. when gate ramps past the v gateh thresh- old at time point 10, pwrgd pulls low. at time point 11, gate reaches its maximum voltage as determined by v in . live insertion with short pin control of uv/ov in the example shown in figure 9, power is delivered through long connector pins whereas the uv/ov divider makes contact through a short pin. this ensures the power connections are firmly established before the ltc4214 is activated. at time point 1, the power pins make contact and v in ramps through v lko . at time point 2, the uv/ov divider
ltc4214-1/ltc4214-2 21 421412f applicatio s i for atio wu u u figure 9. power-up timing with a short pin (all waveforms are referenced to v ee ) makes contact and its voltage exceeds v uvhi . in addition, the internal logic checks for ov < v ovhi , gate < v gatel , sense < v cb , ss < 20 ? v os and timer < v tmrl . if all conditions are met, an initial timing cycle starts and the timer capacitor is charged by a 5 m a current source pull- up. at time point 3, timer reaches the v tmrh threshold and the initial timing cycle terminates. the timer capaci- tor is quickly discharged. at time point 4, the v tmrl threshold is reached and the conditions of gate < v gatel , sense < v cb and ss < 20 ? v os must be satisfied before a gate start-up cycle begins. ss ramps up as dictated by r ss ?c ss ; gate is held low by the analog current limit amplifier until ss crosses 20 ? v os . upon releasing gate, 50 m a sources into the external mosfet gate and com- pensation network. when the gate voltage reaches the mosfets threshold, current begins flowing into the load capacitor at time point 5. at time point 6, load current reaches the ss control level and the analog current limit loop activates. between time points 6 and 8, the gate voltage is servoed, the sense voltage is regulated at v acl (t) and soft-start limits the slew rate of the load current. if the sense voltage (v sense C v ee ) reaches the v cb threshold at time point 7, the circuit breaker timer activates. the timer capacitor, c t , is charged by a 5 a 5 0 a 5 a 5 a 5 0 a g a t e s t a r t - u p i n i t i a l t i m i n g u v c l e a r s v u v h i , c h e c k o v < v o v h i , g a t e < v g a t e l , s e n s e < v c b , s s < 2 0 v o s a n d t i m e r < v t m r l 1 2 3 4 5 6 7 8 9 t i m e r c l e a r s v t m r l , c h e c k g a t e < v g a t e l , s e n s e < v c b a n d s s < 2 0 v o s 1 0 1 1 4 2 1 4 f 0 9 g n d ( 1 2 v ) u v / o v v i n t i m e r g a t e s e n s e v o u t s s d r a i n p w r g d v l k o v u v h i v a c l v c b 4 0 a + 8 i d r n 2 0 v o s v i n v g a t e h v d r n l v d r n c l 2 0 ( v c b + v o s ) 2 0 ( v a c l + v o s ) v g a t e l v t m r l v t m r h
ltc4214-1/ltc4214-2 22 421412f figure 10. undervoltage timing (all waveforms are referenced to v ee ) applicatio s i for atio wu u u (40 m a + 8 ? i drn ) current pull-up. as the load capacitor nears full charge, load current begins to decline. at point 8, the load current falls and the sense voltage drops below v acl (t). the analog current limit loop shuts off and the gate pin ramps further. at time point 9, the sense voltage drops below v cb and the fault timer cycle ends, followed by a 5 m a discharge cycle (cool off). when gate ramps past v gateh threshold at time point 10, pwrgd pulls low. at time point 11, gate reaches its maximum voltage as determined by v in . undervoltage timing in figure 10 when the uv pin drops below v uvhi C v uvhst (time point 1), the ltc4214 shuts down with timer, ss and gate all pulling low. if current has been flowing, the sense pin voltage decreases to zero as gate collapses. when uv recovers and clears v uvhi (time point 2), an initial timer cycle begins followed by a start-up cycle. u v t i m e r g a t e s e n s e s s d r a i n p w r g d 5 a 5 0 a 5 a 5 a 5 0 a u v d r o p s b e l o w v u v h i v u v h s t . g a t e , s s a n d t i m e r a r e p u l l e d d o w n , p w r g d r e l e a s e s 1 2 3 4 5 6 7 8 9 t i m e r c l e a r s v t m r l , c h e c k g a t e < v g a t e l , s e n s e < v c b a n d s s < 2 0 v o s 1 0 1 1 4 2 1 4 f 1 0 u v c l e a r s v u v h i , c h e c k o v c o n d i t i o n , g a t e < v g a t e l , s e n s e < v c b , s s < 2 0 v o s a n d t i m e r < v t m r l v a c l v c b 4 0 a + 8 i d r n 2 0 v o s v i n v g a t e h v d r n l v d r n c l 2 0 ( v c b + v o s ) 2 0 ( v a c l + v o s ) v g a t e l v t m r l v t m r h v u v h i v u v h i v u v h s t g a t e s t a r t - u p i n i t i a l t i m i n g
ltc4214-1/ltc4214-2 23 421412f applicatio s i for atio wu u u figure 11. undervoltage timing with an overvoltage glitch (all waveforms are referenced to v ee ) v in undervoltage lockout timing the v in undervoltage lockout comparator, uvlo, has a similar timing behavior as the uv pin timing except it looks for v in < (v lko C v lkh ) to shut down and v in > v lko to start. in an undervoltage lockout condition, both uv and ov comparators are held off. when v in exits undervoltage lockout, the uv and ov comparators are enabled. undervoltage timing with overvoltage glitch in figure 11, both uv and ov pins are connected together. when uv clears v uvhi (time point 1), an initial timing cycle starts. if the system bus voltage overshoots v ovhi as shown at time point 2, timer discharges. at time point 3, the supply voltage recovers and drops below the v ovhi C v ovhst threshold. the initial timing cycle restarts, followed by a gate start-up cycle. u v / o v t i m e r g a t e s e n s e s s d r a i n p w r g d 5 a 5 0 a 5 0 a 5 a 5 a u v / o v c l e a r s v u v h i , c h e c k o v c o n d i t i o n , g a t e < v g a t e l , s e n s e < v c b , s s < 2 0 v o s a n d t i m e r < v t m r l 1 2 3 4 5 6 7 8 9 t i m e r c l e a r s v t m r l , c h e c k g a t e < v g a t e l , s e n s e < v c b a n d s s < 2 0 v o s 1 0 1 1 1 2 4 2 1 4 f 1 1 u v / o v d r o p s b e l o w v o v h i v o v h s t a n d t i m e r r e s t a r t s i n i t i a l t i m i n g c y c l e u v / o v o v e r s h o o t s v o v h i a n d t i m e r a b o r t s i n i t i a l t i m i n g c y c l e v a c l v c b 4 0 a + 8 i d r n 2 0 v o s v i n v g a t e h v d r n l v d r n c l 2 0 ( v c b + v o s ) 2 0 ( v a c l + v o s ) v g a t e l v t m r l v t m r h v o v h i v u v h i v o v h i v o v h s t g a t e s t a r t - u p i n i t i a l t i m i n g
ltc4214-1/ltc4214-2 24 421412f applicatio s i for atio wu u u figure 12. overvoltage timing (all waveforms are referenced to v ee ) o v t i m e r g a t e s e n s e s s 5 a 5 0 a 5 0 a 5 a 1 2 3 4 5 6 7 8 9 4 2 1 4 f 1 2 o v d r o p s b e l o w v o v h i v o v h s t , c h e c k g a t e < v g a t e l , s e n s e < v c b a n d s s < 2 0 v o s o v o v e r s h o o t s v o v h i . g a t e a n d s s a r e p u l l e d d o w n , p w r g d a n d t i m e r a r e u n a f f e c t e d v a c l v c b 4 0 a + 8 i d r n 2 0 v o s v i n v g a t e h 2 0 ( v c b + v o s ) 2 0 ( v a c l + v o s ) v g a t e l v o v h i v t m r h g a t e s t a r t - u p v o v h i v o v h s t overvoltage timing during normal operation, if the ov pin exceeds v ovhi as shown at time point 1 of figure 12, the timer and pwrgd status are unaffected. nevertheless, ss and gate pull down and the load is disconnected. at time point 2, ov recovers and drops below the v ovhi C v ovhst threshold. a gate start-up cycle begins. if the overvoltage glitch is long enough to deplete the load capacitor, a full start-up cycle as shown between time points 4 through 7 may occur.
ltc4214-1/ltc4214-2 25 421412f applicatio s i for atio wu u u figure 13. circuit-breaker timing behavior (all waveforms are referenced to v ee ) c b f a u l t t i m e r g a t e s e n s e v o u t s s d r a i n p w r g d t i m e r g a t e s e n s e v o u t s s d r a i n p w r g d t i m e r g a t e s e n s e v o u t s s d r a i n p w r g d c b f a u l t c b f a u l t c b f a u l t 5 a 5 a 1 2 4 2 1 4 f 1 3 1 2 c b t i m e s o u t 1 4 3 2 c b t i m e s o u t v a c l v c b v a c l v d r n c l v c b v a c l v t m r h v t m r h v t m r h v c b 4 0 a + 8 i d r n v d r n c l 4 0 a + 8 i d r n 4 0 a + 8 i d r n 4 0 a + 8 i d r n circuit breaker timing in figure 13a, the timer capacitor charges at 40 m a if the sense pin exceeds v cb but v drn is less than 4.2v. if the sense pin drops below v cb before timer reaches the v tmrh threshold, timer is discharged by 5 m a. in figure 13b, when timer exceeds v tmrh , gate pulls down immediately and the ltc4214 shuts down. in figure 13c, multiple momentary faults cause the timer capacitor to integrate and reach v tmrh . gate pull down follows and the ltc4214 shuts down. during shutdown, the ltc4214-1 latches timer high with a 5 m a pull-up current source; the ltc4214-2 activates a shutdown cooling cycle. (13a) momentary circuit-breaker fault (13b) circuit-breaker time out (13c) multiple circuit-breaker fault
ltc4214-1/ltc4214-2 26 421412f applicatio s i for atio wu u u resetting a fault latch (ltc4214-1) the latched circuit breaker fault of ltc4214-1 benefits from long cooling time. it is reset by pulling the uv pin below v uvhi C v uvhst with a switch. reset is also accom- plished by pulling the v in pin momentarily below (v lko C v lkh ). a third reset method involves pulling the timer pin below v tmrl as shown in figure 14. an initial timing cycle is skipped if timer is used for reset. an initial timing cycle is generated if reset by the uv pin or the v in pin. figure 14. pushbutton reset of ltc4214-1s latched fault (all waveforms are referenced to v ee ) the duration of the timer reset pulse should be smaller than the time taken to reach 0.2v at ss pin. with a single pole mechanical pushbutton switch, this may not be feasible. a double pole, single throw pushbutton switch removes this restriction by connecting the second switch to the ss pin. with this method, both the ss and timer pins are released at the same time. t i m e r g a t e s e n s e v a c l v c b s s d r a i n 4 0 a + 8 i d r n v i n v g a t e h v d r n l 4 2 1 4 f 1 4 v d r n c l v g a t e l v t m r l v t m r h p w r g d 5 a 5 a 5 a 5 0 a 5 0 a 1 2 3 4 5 6 7 8 9 s w i t c h r e l e a s e s s s s w i t c h r e s e t s l a t c h e d t i m e r g a t e s t a r t - u p 2 0 v o s 2 0 ( v c b + v o s ) 2 0 ( v a c l + v o s ) m o m e n t a r y d p s t s w i t c h r e s e t
ltc4214-1/ltc4214-2 27 421412f applicatio s i for atio wu u u shutdown cooling cycle (ltc4214-2) figure 15 shows the timer behavior of the ltc4214-2. at time point 2, timer exceeds v tmrh , gate pulls down immediately and the ltc4214 shuts down. timer starts a shutdown cooling cycle by discharging timer with 5 m a to the v tmrl threshold. timer then charges with 5 m a to the v tmrh threshold. there are four 5 m a discharge phases figure 15. shutdown cooling timing behavior of ltc4214-2 (all waveforms are referenced to v ee ) and three 5 m a charge phases in this shutdown cooling cycle spanning time points 2 and 3. at time point 3, the ltc4214 automatic retry occurs with a start-up cycle. good thermal management techniques are highly recom- mended; power and thermal dissipation must be carefully evaluated when implementing the automatic retry scheme. t i m e r g a t e s e n s e v o u t v a c l v c b s s d r a i n 4 0 a + 8 i d r n v t m r h v t m r l v g a t e l 4 0 a + 8 i d r n v i n v g a t e h v d r n l 4 2 1 4 f 1 5 v d r n c l p w r g d 5 0 a 5 0 a 5 a 5 a 5 a 5 a 5 a 5 a 5 a 5 a 5 a g a t e s t a r t - u p s h u t d o w n c o o l i n g c b 2 0 v o s 2 0 ( v c b + v o s ) 2 0 ( v a c l + v o s ) 1 2 3 4 5 6 7 8 9 1 0 r e t r y c i r c u i t b r e a k e r t i m e s o u t
ltc4214-1/ltc4214-2 28 421412f applicatio s i for atio wu u u figure 16. current limit behavior (all waveforms are referenced to v ee ) (16a) analog current limit fault (16b) fast current limit fault analog current limit and fast current limit in figure 16a, when sense exceeds v acl , gate is regu- lated by the analog current limit amplifier loop. when sense drops below v acl , gate is allowed to pull up. in figure 16b, when a severe fault occurs, sense exceeds v fcl and gate immediately pulls down until the analog current amplifier can establish control. if the severe fault causes v out to exceed v drncl , the drain pin is clamped at v drncl . i drn flows into the drain pin and is multiplied by 8. this extra current is added to the timer pull-up current of 40 m a. this accelerated timer current of [40 m a+8 ? i drn ] produces a shorter circuit breaker fault delay. careful selection of c t , r d and mosfet can help prevent soa damage in a low impedance fault condition. t i m e r g a t e s e n s e v o u t v a c l v c b s s d r a i n v t m r h 4 0 a + 8 i d r n 4 2 1 4 f 1 6 p w r g d 5 a 5 a t i m e r g a t e s e n s e v o u t v a c l v c b v f c l s s d r a i n v t m r h v d r n c l 4 0 a + 8 i d r n p w r g d 1 2 1 4 3 2 c b t i m e s o u t
ltc4214-1/ltc4214-2 29 421412f soft-start if the ss pin is not connected, this pin defaults to a linear voltage ramp, from 0v to 1.6v in about 220 m s at gate start-up, as shown in figure 17a. if a soft-start capacitor, c ss , is connected to this ss pin, the soft-start response is modified from a linear ramp to an rc response (equa- tion 6), as shown in figure 17b. this feature allows load current to slowly ramp-up at gate start-up. soft-start is initiated at time point 3 by a timer transition from v tmrh to v tmrl (time points 1 to 2) or by the ov pin falling below the v ovhi C v ovhst threshold after an ov condition. when the ss pin is below 0.2v, the analog current limit amplifier holds gate low. above 0.2v, gate is released and 50 m a ramps up the compensation network and gate capaci- tance at time point 4. meanwhile, the ss pin voltage continues to ramp up. when gate reaches the mosfets threshold, the mosfet begins to conduct. due to the mosfets high g m , the mosfet current quickly reaches the soft-start control value of v acl (t) (equation 7). at time point 6, the gate voltage is controlled by the current limit amplifier. the soft-start control voltage reaches the circuit breaker voltage, v cb , at time point 7 and the circuit breaker timer activates. as the load capacitor nears full charge, load current begins to decline below v acl (t). the current limit loop shuts off and gate releases at time point 8. at time point 9, the sense voltage falls below v cb and timer deactivates. large values of c ss can cause premature circuit breaker time out as v acl (t) may exceed the v cb potential during the circuit breaker delay. the load capacitor is unable to achieve full charge in one gate start-up cycle. a more serious side effect of large c ss values is soa duration may be exceeded during soft-start into a low impedance load. a soft-start voltage below v cb will not activate the circuit breaker timer. figure 17. soft-start timing (all waveforms are referenced to v ee ) (17a) without external c ss (17b) with external c ss applicatio s i for atio wu u u t i m e r g a t e s e n s e s s d r a i n v t m r h v d r n c l v a c l v c b v d r n l v g s ( t h ) v i n v g a t e h v t m r l 4 0 a + 8 i d r n 4 2 1 4 f 1 7 p w r g d 5 a 5 0 a 5 0 a t i m e r g a t e s e n s e s s d r a i n v t m r h v d r n c l v c b v a c l v d r n l v g s ( t h ) v i n v g a t e h v t m r l 4 0 a + 8 i d r n p w r g d 5 a 5 0 a 5 0 a 1 2 3 4 5 6 7 7 a 8 9 1 0 1 1 e n d o f i n t i a l t i m i n g c y c l e 1 2 3 4 5 6 7 8 9 1 0 1 1 e n d o f i n t i a l t i m i n g c y c l e 2 0 v o s 2 0 ( v c b + v o s ) 2 0 ( v a c l + v o s ) 2 0 v o s 2 0 ( v c b + v o s ) 2 0 ( v a c l + v o s )
ltc4214-1/ltc4214-2 30 421412f figure 18. power limit circuit breaking application applicatio s i for atio wu u u 4214 f18 gnd uv z1 ov v ee v in sense ss timer gate pwrgd drain ltc4214-1 r1 124k 1% r x 10 c x 100nf r2 3.65k 1% r3 32.4k 1% c t 47nf c ss 22nf c c 10nf C12v r s 0.025 q1 irf7413 q2 2n2222 v out gnd r c 10 r4 5.6k r in 470 d1 bzx84c10 d2 1n4148 1 9 8 10 3 2 7 6 4 5 c1 1nf c in 0.1 f c l 100 f r pullup v logic gnd (short pin) + r d 475k r6 20 en z1: smaj15a r5 10k power limit circuit breaker figure 18 shows the ltc4214-1 in a power limit circuit breaking application. the sense pin is modulated by the board supply voltage, v supply . the zener voltage, v z is set to be the same as the low supply operating voltage, v supply(min) = 10v. if the goal is to have the high supply operating voltage, v supply(max) = 14v give the same power at v supply(min) , then resistors r4 and r6 are selected using the ratio: r r v v cb supply max 6 4 = () (16) if r6 is 20 w , r4 is 5.6k. the peak circuit breaker power limit is: power vv vv power power max supply min supply max supply min supply max supply min supply min = + () = () ( ) () ( ) () () . 2 4 1 029 (17) when v supply = 0.5 ? (v supply(min) + v supply(max) ) = 12v. the peak power at the fault current limit occurs at the supply overvoltage threshold. the fault current limited power is: power v r vv v r r fault supply s acl supply z = () ? ? ? ? 6 4 (18)
ltc4214-1/ltc4214-2 31 421412f ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661) package descriptio u msop (ms) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 0.27 (.007 ?.011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
ltc4214-1/ltc4214-2 32 421412f gate 5v/div sense 50mv/div v out 10v/div pwrgd 10v/div 4214 ta03 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2002 lt/tp 0204 1k printed in usa related parts part number description comments ltc1421 two channels, hot swap controller operates from 3v to 12v and supports C12v ltc1642 fault protected hot swap controller 3v to 16.5v, overvoltage protection up to 33v ltc1644 pci hot swap controller 3.3v, 5v and 12v; 1v precharge; pci reset logic ltc4210 hot swap controller in sot-23 active current limiting, 2.7v to 16.5v ltc4211 single hot swap with multifunction current control operates from 2.5v to 16.5v lt4220 dual hot swap controller for positive/negative supplies operates from 2.7v to 16.5v ltc4230 triple hot swap controller with multifunction current control operates from 1.7v to 16.5v typical applicatio u figure 19. C 12v/2a hot swap controller 4214 f19 gnd ov uv v ee v in sense ss timer gate pwrgd drain ltc4214-1 r1 121k 1% r x 10 r in 470 z1 c x 100nf r2 32.4k 1% c t 47nf c ss 22nf c c 10nf ?2v r s 0.025 q1 irf7413 v out gnd controller v ee r c 10 r3 5.1k 1 8 9 10 3 2 7 6 4 5 c1 1nf c in 0.1 f c l 100 f gnd (short pin) + r d 475k en *m0c207 z1:smaj15a * start-up behavior

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